The present invention relates to a semiconductor memory, a method of testing the same, and a method of manufacturing the same, and particularly to a technology effective for application to testing and manufacture of an electrically programmable and erasable nonvolatile semiconductor memory like a flash memory, and an electrically programmable and erasable nonvolatile semiconductor memory with a test circuit built therein.
As a method of testing a semiconductor memory, there is generally provided a method of generating test pattern data by a test device called a memory tester, inputting the test data to a memory to thereby perform its writing, next reading the written data from the memory, comparing the data with an expected value, and thereby determining the memory as defective when they do not coincide with each other.
In a volatile semiconductor memory such as a DRAM (Dynamic Random Access Memory), an SRAM (Static RAM) or the like, a so-called repair technology based on a redundant circuit system has been established in which a spare memory column or memory row is provided and when a fail bit is detected, its corresponding substitution is performed. In an electrically programmable and erasable nonvolatile semiconductor memory typified by a flash memory, contrary to the above, there is known a technology for configuring a system in such a manner that a failure address is detected by testing, and the detected non-failure/failure information is stored in a memory array and provided for a user, and the user avoids a fail bit through the use of the non-failure/failure information and makes use of a normal bit alone.
Further, in the volatile semiconductor memory such as the DRAM, SRAM or the like, there has been proposed the invention related to a semiconductor memory wherein a test circuit called an ALPG (Algorithmic Memory Pattern Generator) for generating test patterns (addresses and data) of a memory circuit in accordance with a predetermined algorithm and performing its test is mounted on a semiconductor chip equipped with the memory circuit (International Publication WO98/47152).
Such a test technology of ALPG system can be also applied to a nonvolatile semiconductor memory. Since, however, the flash memory or the like needs a mechanism for detecting the failure address by testing and storing the detected non-failure/failure information in the memory array as described above, it has been considered that the flash memory or the like encounters difficulties in providing the test circuit on the chip and performing its testing.
On the other hand, a test placed under a high temperature called a burn-in test or an aging test for detecting potential defective units in addition to a tester-based inspection at a wafer stage has been also performed upon testing of the semiconductor memories including the nonvolatile memory such as the flash memory or the like as well as the DRAM and SRAM. The burn-in test is performed while mounting several tens to several hundreds of memories each placed in a state of being assembled into a package, onto a printed board called a burn-in board, collectively inserting the board into a heating chamber in the form of several tens of sheets and applying test patterns from a control device.
The nonvolatile semiconductor memory encounters difficulties in stabilizing write and erase characteristics in the case of the present process technology. Therefore, a write and erase-repeated write/erase cycle test unexecuted upon testing of the volatile semiconductor memory such as the DRAM (Dynamic Random Access Memory), the SRAM (Static RAM) or the like, has been performed within a burn-in apparatus.
FIG. 10 shows a procedure for testing a conventional nonvolatile semiconductor memory after the assembly thereof into a package. As shown in the same drawing, memories subsequent to the completion of an assembly step of Step S1 are shifted to a burn-in step (Step S2), where they are respectively mounted onto a burn-in board and subjected to a burn-in test in normally several hundreds of units over 10 hours or so. Further, a write and erase-repeated write/erase cycle test is performed within the burn-in apparatus (Step S3). Afterwards, the procedure proceeds to a sorting or selection step (Step S4) using a memory tester, where a DC test, an AC test and a function test, etc. are performed, whereby only ones judged as non-defective are shipped.
However, the conventional test method is accompanied by a problem that since the tests using the memory tester can be performed only in a few or several tens of units, they are inefficient as compared with the burn-in apparatus capable of performing tests in several thousands of units, and since an expensive tester capable of performing the function test is required in the selection step in Step S4, the rate of a test cost taken up in a product unit price becomes so high.
Described specifically, the cost of the tester capable of performing the function test takes several tens of times as much in cost as the most expensive device with a test function, of a tester and a burn-in apparatus capable of performing a DC test and an AC test alone. Since the conventional test method makes use of such an expensive tester and can be executed only in the few or several tens of units, the number of testers is limited even if the efficiency of a manufacturing process is made high. Therefore, the time required to perform each test by the tester was brought into a bottleneck, so that production efficiency was remarkably reduced. Since the number of expensive testers must be increased to increase the number of memories testable per unit time, a problem arises in that a huge or tremendous capital investment is required.
An object of the present invention is to provide a test technology capable of testing a nonvolatile semiconductor memory without using such an expensive tester as to be capable of performing a function test.
Another object of the present invention is to provide a test technology capable of increasing the number of nonvolatile semiconductor memories capable of simultaneously performing a function test.
A further object of the present invention is to provide a test technology capable of causing a nonvolatile semiconductor memory to perform its self-test without increasing a chip size so much.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of representative ones of the inventions disclosed in the present application will be described as follows:
A method of testing a plurality of semiconductor memories to be tested, according to the present invention, is characterized by mounting the plurality of semiconductor memories on a printed board or a test board equipped with a plurality of sockets in which the plurality of semiconductor memories are mountable, and testing circuits each including a comparator for comparing data read from the semiconductor memories with expected value data and thereby detecting coincidences/non-coincidences therebetween and a counter for counting the number of the detected non-coincidences, connecting the printed board to a connector lying within a heating chamber of a burn-in apparatus, simultaneously testing the plurality of semiconductor memories by the testing circuits while updating addresses, and counting the number of addresses at which failures are detected, by the counter and outputting the result of counting thereby.
According to the above configuration, a plurality of semiconductor memories mounted on the same board can be simultaneously tested within a burn-in apparatus by testing circuits on a printed board and the detected result of failure can be outputted. It is therefore possible to eliminate the use of such an expensive tester as to be capable of performing a function test and test a large number of semiconductor memories simultaneously. Consequently, the cost taken for testing can be lowered, and the amount of a capital investment for shorting the time required to perform testing can be reduced.
Preferably, failure information obtained by ORing a previous result of failure determination read from storing means for storing a result of failure determination based on the result of comparison by the comparator with a result of failure/non-failure determination based on the result of comparison by the comparator is stored again in the storing means. Thus, since a plurality of types of tests are continuously performed and their results can be stored in the storing means, test efficiency is enhanced. Since the failure information obtained by making ORing with the previous result of failure determination is stored in the storing means, the memory or storage capacity of the storing means for storing the failure information can be reduced and the cost of each testing circuit can be lowered.
Further, preferably, the failure information read from the storing means for storing the failure information is counted by the counter lying within each testing circuit after the completion of testing. Thereafter, dummy failure information or determining failure information is supplied to and counted by the counter, and an overflow signal outputted from the counter is monitored to make failure/non-failure determination. Consequently, a decision as to whether a product (corresponding to a semiconductor memory configured as a device to be tested) is non-defective or defective, can be simply performed by a simple test device.
Next, a semiconductor memory manufacturing method according to the present invention is characterized by mounting semiconductor memories obtained by cutting memory chips formed on a wafer and enclosing the same in packages on a printed board or a test board equipped with a plurality of sockets, and testing circuits each including a comparator for comparing data read from the semiconductor memories to be tested with expected value data and thereby detecting coincidences/non-coincidences therebetween and a counter for counting the number of the detected non-coincidences, connecting the printed board to a connector lying within a heating chamber of a burn-in apparatus, simultaneously testing the plurality of semiconductor memories by the testing circuits while updating addresses after execution of a burn-in process or while the burn-in process is being performed, thereafter taking out the printed board from within the heating chamber of the burn-in apparatus, performing, by a test device, a test other than the tests executed by the testing circuits, and selecting only the semiconductor memories judged as non-defective by the two tests.
According to the above configuration, since a plurality of semiconductor memories mounted on the same board are simultaneously tested within a burn-in apparatus by testing circuits on a printed board and the detected result of failure can be outputted, the use of such an expensive tester as to be capable of performing a function test becomes unnecessary. Further, since the time required to perform testing can be shortened owing to the execution of simultaneous testing of a large number of semiconductor memories, the manufacturing cost can be drastically reduced.
Further, a semiconductor memory according to the present invention is one configured in such a manner that a testing circuit including a comparator for comparing data read from a memory circuit to be tested with expected value data to thereby detect coincidences/non-coincidences therebetween, and a counter for counting the number of the detected non-coincidences is formed on the same semiconductor chip as one being formed with the memory circuit to be tested, the memory circuit is tested by the testing circuit while updating addresses, the number of addresses at which failures are detected, is counted by the counter, and the result of counting thereby is capable of being outputted to the outside.
According to the above configuration, the memory circuit is tested without using a high-performance tester, so that the presence or absence of each fail bit can be recognized. Thus, the cost taken for testing can be reduced, and a large number of semiconductor memories can be tested simultaneously using a burn-in apparatus or the like, whereby the time required to perform testing can be greatly shortened.
Here, preferably, a result-of-determination storage circuit for storing a result of failure determination based on a result of comparison by the comparator is formed on the same semiconductor chip as one being formed with the memory circuit to be tested, together with the testing circuit. Thus, since there is no need to store the result of testing in an external test device, the management of the test result and the process of product selection or the like based on the management can be easily performed.
Each of word lines for the result-of-determination storage circuit may be configured so as to be selected by a select signal of an address decoder for selecting each word line in a memory array of the memory circuit, and the result of failure determination based on the result of comparison by the comparator may be configured so as to be stored in the result-of-determination storage circuit in association with each memory row of the memory array to be tested. Thus, when the result-of-determination storage circuit for storing the result of failure determination is formed on one semiconductor chip together with the memory circuit and testing circuit, circuit""s simplification is enabled and a substantial increase in chip size can be suppressed.
Further, the result-of-determination storage circuit is provided at part of the memory circuit to be tested. Consequently, further circuit""s simplification is enabled and an increase in chip size can be suppressed. Further, the result-of-determination storage circuit can be built in a chip without any need to add a new step in a process.
Preferably, information obtained by ORing a previous result of failure determination read from the result-of-determination storage circuit with a result of failure/non-failure determination based on the result of comparison by the comparator is configured so as to be stored in the result-of-determination storage circuit. Thus, even when a plurality of types of tests are performed, the memory capacity of the result-of-determination storage circuit for storing their results therein needs not to increase. It is therefore possible to realize a semiconductor memory high in reliability and small in chip size.
Further, preferably, the counter for counting the number of failure addresses is configured so as to count the failure information read from the result-of-determination storage circuit. Thus, since the counting of the number of failure addresses may be once even when a plurality of types of tests are performed, the time required for determination is shortened.
Further, the counter may be configured so as to count the failure information read from the result-of-determination storage circuit and output an overflow signal when the counter counts subsequently-inputted dummy failure information or determining failure information and counts the same up to a predetermined number. Thus, since there is no need to determine the number of failure addresses, and the overflow signal may simply be monitored, the burden on a test device for making a decision is less reduced.
When the memory circuit to be tested comprises nonvolatile memory elements, the result-of-determination storage circuit may be made of volatile memory elements. Since the storage circuit made of the volatile memory elements is short in write time as compared with the storage circuit comprising the nonvolatile memory elements, an increase in test time can be suppressed where the storage circuit for storing the result of determination is built in a chip.